Referring to FIG. 1, a diagram illustrating a conventional dynamic random access memory (DRAM) 10 is shown. The conventional DRAM preserves data during periodic absences of power by implementing a memory cell 12 as a capacitor 14 and an access transistor 16. The conventional DRAM uses a single memory cell 12 for each bit of data stored. A sense amplifier 18 compares a signal received from the memory cell 12 via a bitline 20 with a reference signal REF to determine a stored value. The memory cell 12 is accessed using a single wordline 22.
Since the charge on the capacitor 14 will slowly leak away, the cells need to be "refreshed" once every few milliseconds. In order to refresh the cells, the DRAM typically requires an additional cycle. During the normal cycle, the DRAM will read data and write-back data. During a refresh cycle, the DRAM will (i) read data and write-back data as in the normal cycle and (ii) perform another read that is not intended for user access but rather to refresh the read data to prevent degradation. While effectively preserving the data, the additional refresh cycle makes the DRAM slower than a static random access memory (SRAM).
A static random access memory (SRAM) has only one cycle during which the chip either reads data or writes data. The SRAM is generally faster than other types of memory that require multiple cycles. Static random access memory requires more die space and must be constantly powered to maintain stored data.
It would be desirable to have a DRAM that could be refreshed at the same time as a normal access regardless of where the data is to be refreshed or the data to be accessed is stored.